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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74AVCH20T245DGG

20-bit dual supply translating transceiver with configurable voltage translation; 3-state

The 74AVCH20T245 is a 20-bit, dual supply transceiver that enables bi-directional voltage level translation. The device can be used as two 10-bit transceivers or as a single 20-bit transceiver. It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output enable inputs (nOE), two direction inputs (nDIR) and dual supplies (VCC(A) and VCC(B)). VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for bi?-?directional voltage level translation between any of the low voltage nodes: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, nOE and nDIR are referenced to VCC(A), the 1Bn and 2Bn ports are referenced to VCC(B). A HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to assume a HIGH impedance OFF-state.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all output ports will assume a high impedance OFF-state. The bus hold circuitry on the powered-up side always stays active.

The 74AVCH20T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Features and benefits

  • Wide supply voltage range: VCC(A): 0.8 V to 3.6 V; VCC(B): 0.8 V to 3.6 V

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Maximum data rates:

    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

    • 260 Mbit/s (≥ 1.1 V to 3.3 V translation)

    • 260 Mbit/s (≥ 1.1 V to 2.5 V translation)

    • 210 Mbit/s (≥ 1.1 V to 1.8 V translation)

    • 120 Mbit/s (≥ 1.1 V to 1.5 V translation)

    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

  • Suspend mode

  • Bus hold on data inputs

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數類型

型號 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Package name Category
74AVCH20T245DGG 0.8?-?3.6 0.8?-?3.6 CMOS/LVTTL ± 12 2.1 20 very low -40~125 93 21 TSSOP56 Bi-directional | Direction controlled

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74AVCH20T245DGG 74AVCH20T245DGG,11
(935286236118)		 Active AVCH20T245 SOT364-1
TSSOP56
(SOT364-1) 		SOT364-1 SSOP-TSSOP-VSO-WAVE
SOT364-1_118

環(huán)境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74AVCH20T245DGG 74AVCH20T245DGG,11 74AVCH20T245DGG rohs rhf rhf
品質及可靠性免責聲明

文檔 (9)

文件名稱 標題 類型 日期
74AVCH20T245 20-bit dual supply translating transceiver with configurable voltage translation; 3-state Data sheet 2024-06-25
AN90007 Pin FMEA for AVC family Application note 2018-11-30
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT364-1 plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body Package information 2022-06-23
SOT364-1_118 TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation Packing information 2020-04-21
74AVCH20T245DGG_Nexperia_Product_Reliability 74AVCH20T245DGG Nexperia Product Reliability Quality document 2024-06-16
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱 標題 類型 日期
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74AVCH20T245DGG 74AVCH20T245DGG,11 935286236118 Active SOT364-1_118 2,000 訂單產品

樣品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經銷商處購買
74AVCH20T245DGG 74AVCH20T245DGG,11 935286236118 SOT364-1 訂單產品